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MoSys Patents
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From the beginning, MoSys has been a leading technological innovator, and the company’s large engineering team has built an extensive patent portfolio. The company has more than 97 U.S. and 72 foreign patents and patents pending, representing over 500 staff-years of research and development.
Below are some examples of current MoSys patents. (Includes patents originally awarded to Atmos Corp., acquired by MoSys in 2002.)
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US Patent # |
Patent Description |
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1
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High Density SRAM Circuit with Single-Ended Memory Cells |
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2
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Circuit Module Redundancy Architecture |
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3
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Reduced CMOS-Swing Clamping Circuit for Bus Lines |
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4
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Pseudo-Nonvolatile Memory Incorporating Data Refresh Operation |
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5
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Wafer-Scale Integrated Circuit Interconnect Structure Architecture |
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6
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Defect Tolerant Integrated Circuit Subsystem for Communications between a Module and a Bus Controller |
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7
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Method and Circuit for Communication between a Module and a Bus Controller in a Wafer-Scale IC System |
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8
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Method and Structure for Controlling Internal Operations of a DRAM Array |
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9
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Resynchronization Circuit for a Memory System and Method of Operating Same |
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10
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Fault-Tolerant Hierarchical Bus System and Method of Operating Same |
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11
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Method and Structure for Generating a Boosted Word Line Voltage and a Back Bias Voltage for a Memory Array |
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12
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Method and Structure for Controlling Internal Operations of a DRAM array |
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13
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Termination Circuit for Reduced Swing Signal Lines and Methods for Operating Same |
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14
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Resynchronization Circuit for Circuit Module Architecture |
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15
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Method and Structure for Performing Pipeline Burst Accesses in a Semiconductor Memory |
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16
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Caching Method and Circuit for a Memory System with Circuit Module Architecture |
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17
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Method and Structure for Improving Display Data Bandwidth in a UMA System |
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18
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Method and Structure for Generating a Boosted Word Line Voltage and a Back Bias Voltage for a Memory Array |
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19
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Method and Structure for Implementing a Cache Memory Using a DRAM Array |
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20
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Termination Circuit with Power-Down Mode for Use in a Circuit Module Architecture |
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21
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Circuit Module Redundancy Architecture Process |
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22
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Multiport DRAM Cell and Memory System Using Same |
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23
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Method and Structure for Data Traffic Reduction for Display Refresh |
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24
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Method and Apparatus for DRAM Refresh Using Master, Slave and Self-Refresh Modes |
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25
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Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory |
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26
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Caching in a Multi-Processor Computer System |
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27
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Method and Apparatus for 1T-SRAM Compatible Memory |
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28
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Memory Cell for DRAM Embedded in Logic |
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29
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Method and Apparatus for Increasing the Time Available for Refresh for 1T-SRAM Compatible Devices |
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30
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Method and Structure for Controlling Operation of a DRAM Array |
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31
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System Utilizing a DRAM Array as a Next Level Cache Memory and Method for Operating Same |
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32
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Clock Phase Generator for Controlling Operations of a DRAM Array |
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33
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On-chip Word Line Voltage Generation for DRAM Embedded in Logic Process |
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34
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Method and Apparatus for Maximizing the Random Access Bandwidth of a Multi-Bank DRAM in a Computer |
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35
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Method and Apparatus for Refreshing A Semiconductor Memory Using Idle Memory Cycles |
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36
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Method and Apparatus for Increasing the Time Available for Internal Refresh for 1T-SRAM Compatible Devices |
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37
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Method for Generating a Clock Phase Signal for Controlling Operation of a DRAM Array |
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38
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Data Processing System with Master and Slave Devices and Assymetric Signal Swing Bus |
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39
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Method of Operating Memory Array with Write Buffers and Related Apparatus |
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40
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High-Speed Read-Write Circuitry for Semiconductor Memory |
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41
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Non-Volatile Memory Cell and Methods Of Fabricating and Operating Same |
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42
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Method and Structure of Ternary Cam Cell in Logic Process |
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43
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Single-Port Multi-Bank Memory System Having Read and Write Buffers and Method of Operating Same |
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44
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Dynamic Address Mapping and Redundancy in a Modular Memory Device |
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45
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Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same |
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46
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Method for Using a Latched Sense Amplifier in a Memory Module as a High-Speed Cache Memory |
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47
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High Density Ratio Independent Four Transistor RAM Cell Fabricated with a Conventional Logic Process |
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48
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Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same |
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49
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Method of Operating a System-on-a-Chip Including Entering a Standby State in a Non-Volatile Memory |
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50
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Reduced Topography DRAM Cell Fabricated Using a Modified Logic Process and Method for Operating Same |
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51
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Memory Module with High-Speed Latched Sense Amplifiers |
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52
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Method and Apparatus for Forcing Idle Cycles to Enable Refresh Operations in a Semiconductor Memory |
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53
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Method and Apparatus for Completely Hiding Refresh Operations in a DRAM Device Using Clock Division |
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54
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DRAM Cell Fabricated Using a Modified Logic Process and Method for Operating Same |
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55
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Apparatus for Controlling Data Transfer between a Bus and Memory Array and Method for Operating Same |
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56
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Non-Volatile Memory Embedded in a Conventional Logic Process |
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57
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RAM Having Dynamically Switchable Access Modes |
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58
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DRAM Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same |
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59
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SRAM Emulator |
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60
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Twisted Wordline Strapping Arrangement |
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61
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DRAM Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same |
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62
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Reduced Topography DRAM Cell Fabricated Using a Modified Logic Process and Method for Operating Same |
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63
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One-Transistor Floating-Body DRAM Cell in Bulk CMOS Process with Electrically Isolated Charge Storage Unit |
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64
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Vertical One-Transistor Floating-Body DRAM Cell In Bulk CMOS Process With Electrically Isolated Charge Storage Region |
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65
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Method and Apparatus for Completely Hiding Refresh Operations in a DRAM Device Using Clock Division |
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66
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High Speed Read-Write Circuitry For Semi-Conductor Memory Device |
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67
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Latched Sense Amplifier As High Speed Memory In A Memory System |
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68
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Method And Apparatus For Memory Redundancy With No Critical Delay-Path |
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69
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DRAM Cell Having A Capacitor Fabricated Partially In A Cavity And Method For Operating Same |
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70
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Method and Apparatus for Completely Hiding Refresh Operations in a DRAM Device Using Clock Division |
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71
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Memory Array With Read/Write Methods |
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72
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Method Of Fabricating A DFRAM Cell Having a Thin Dielectric Storage Capacitor |
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73
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Method And Apparatus For Lengthening The Data-Retention Time Of A DRAM Device In Standby Mode |
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74
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Non-Volatile Memory With Crown Electrode To Increase Capacitance Between Control Gate and Floating Gate |
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75
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Non-Volatile Memory Cell Fabricated With Slight Modification to a Conventional Logic Process And Method of Operating Same |
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76
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Method and Apparatus for Temperature Adaptive Refresh in 1T-SRAM Compatible Memory Using Subthreshold Characteristics of MOSFET Transistors |
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77
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Method of Fabrication A Transistor Floating-Body DRAM Cell In a Bulk CMOS Process With Electrically Isolated Charge Storage Region |
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78
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Method of Fabricating Vertical One-Transistor Floating-Body DRAM Cell In Bulk CMOS Process with Electrically Isolated Charge Storage Region |
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79
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Error correcting memory and method of operating same |
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